It is usual nowadays, in a system having one or more transmitting locations and several receiving locations, to send a signal transmitted from a transmitting location to all receiving locations via a common transmission channel, for instance in the form of a bus line. For providing the possibility of sending a message from the transmitting location to only one receiving location, the signals transmitted to the receiving location each contain an address word in addition to the message to be transferred. Each of the receiving locations has at least one specific address word associated therewith. The individual receiving locations comprise devices for the selection of the respective address words associated therewith. The receiving location for which the particular message is intended can thus take such messages from the transmission channel which are provided with a data word that is intended for or acceptable to these receiving locations.
If several receivers belong to one receiving location, it is possible to associate an address word of its own with each of these receivers. If certain messages shall be receivable by several receiving locations, this may be accomplished in that each of these receiving locations not only accepts its own address word but also additional address words. In these cases, the receiving location will be designed such that it is adapted to accept several address words.
To determine whether the address word of the message transmitted over the transmission channel, for instance the bus line, is intended for a specific receiving location or not, the address word of the message is compared in the receiving location with the address word or words associated with this receiving location. This takes place conventionally by means of filters having, just as the address words, n bit locations, in which a bit sequence is deposited corresponding to the bit sequence of an acceptable address word. If the particular receiving location is to be capable of accepting several address words, it requires as many filters with n bit locations each as there are acceptable address words. The address word of each message offered to the individual receiving location is compared with each bit sequence in each filter of this receiving location for conformity or nonconformity. If there is conformity, the just received address word is accepted and the message added to this address is allowed to pass to load units of this receiving location. If the just received address word is not in conformity with the bit sequence deposited in one of the filters, this address word is not accepted and the message accompanying this address word does not reach load units of this receiving location.
If in the known acceptance examination method, for example four different address words are to be accepted for one specific receiving location, four filters must be provided in this receiving location each having a filter length equal to the address word length. With an address word length of for instance eight bit locations, 32 filter locations are required in this case. In addition thereto, one needs a correspondingly large number of word lines with a correspondingly high space requirement on the semiconductor chip on which the address selection device is provided.
To determine whether or not a received address word is in conformity with the bit sequence deposited in the filter, XOR gate circuits are conventionally used, namely one such circuit for each bit location of address word and filter. For example, when the address word has eight bit locations, the filter has also eight bit locations, and eight XOR gate circuits are necessary for the comparison of the received address with the bit sequence stored in the filter. The outputs of all XOR elements are passed to an OR element having as many inputs as there are XOR elements. At an output of the OR element, the logic value "0" or the logic value "1" appears, depending on whether or not there is conformity between the just received address word and the word stored in the filter. The logic value "0" at the output of the OR element means thus that the just received address word is accepted by the receiving location in consideration, whereas it is not accepted when the logic value "1" appears at the output of the OR element.
In case of the above-considered conventional solution, each one of the several filters of a receiving location has a filter length equal to the address word length. This requires hardware with a capacity which one possibly would not like to provide for reasons of costs. On the other hand, many word lines are necessary between the address register, in which the address for the filter comparison is stored temporarily, the filters, the XOR elements used for the comparison and the OR element coupled downstream thereof. These word lines require a lot of space on a monolithically integrated semiconductor circuit. XOR elements also require relatively large areas on a semiconductor chip.
What is needed is to reduce the circuit expenditure for the acceptance examination of address words received, in particular in such a manner that chip area can be saved.